A High-Speed Low-Power Hybrid Analog-to-Digital Converter for Wireless Portable Medical Devices

In recent years, telemedicine has become popular because it makes access to healthcare more convenient with lower cost, thereby saving lives through early diagnosis and real-time monitoring. The goal of this research is to design a high-speed analog-to-digital converter (ADC) to be used in portable communication chips for telemedicine applications that require low power consumption to extend the lifetimes of batteries. The high-speed and low-power performance is achieved by devising a hybrid architecture that combines the advantages of two different types of ADCs. In the first stage, a flash ADC resolves the three most significant bits of the analog input signal, and the remaining five bits are determined by four time-interleaved low power SAR ADCs in the second stage, leading to an overall hybrid ADC having 8-bit resolution while operating with a 1GHz sampling clock signal. The hybrid ADC was designed and simulated with a mix of behavioral models and transistor-level circuit designs in 130nm CMOS technology. The estimated power consumption is 15mW from a 1.2V supply.

About the author:

Alireza Zahrai is a Ph.D. candidate in Electrical Engineering and research assistant in the Analog & Mixed-Signal Integrated Circuit (AMSIC) Research Laboratory, Northeastern University, Boston. He received his B.Sc. and M.Sc. in Electrical Engineering from the University of Tehran and Iran University of Science and Technology, Tehran, Iran respectively. He was an IC Design Intern at CSR plc, Tempe, AZ in 2013, where he worked on the design of a SAR ADC for an audio SoC. His current research includes low-power high-speed time-interleaving ADC design (GS/s) and on-chip digital calibration systems. His research interests are analog and mixed-signal IC design, high-speed data converters and digitally-assisted analog circuits.